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1 features ? 6.6 spec int 95, 5.5 specfp95 at 266 mhz (estimated) superscalar 603e core integer unit (iu), floating-point unit (fpu) (user enabled or disabled), load/store unit (lsu), system register unit (sru), and a branch processing unit (bpu) 16-kbyte instruction cache 16-kbyte data cache lockable l1 caches - entire cache or on a per-way basis up to 3 of 4 ways dynamic power management high-bandwidth bus (32/64 bits data bus) to dram supports 1-mbyte to 1-gbyte dram memory 32-bit pci interface operating up to 66 mhz pci 2.1-compliant, 5.0v tolerance fint max = 200 mhz fbus max = 66 mhz description the pc8240 combines a powerpc ? 603e core microprocessor with a pci bridge. the pc8240?s pci support will allow system designers to rapidly design systems using peripherals already designed for pci and the other standard interfaces. the pc8240 also integrates a high- performance memory controller which supports various types of dram and rom. the pc8240 is the first of a family of products that provides system level support for industry standard inter- faces with a powerpc microprocessor core. the peripheral logic integrates a pci bridge, memory controller, dma controller, epic interrupt controller, i 2 o controller, and a two-wire interface controller. the 603e core is a full-featured, high-performance processor with floating-point support, memory management, 16-kbyte instruction cache, 16-kbyte data cache, and power management features. the integration reduces the overall packaging requirements and the number of discrete devices required for an embedded system. the pc8240 contains an internal peripheral logic bus that interfaces the 603e core to the peripheral logic. the core can operate at a variety of frequencies, allowing the designer to trade off performance for power consumption. the 603e core is clocked from a separate pll, which is referenced to the peripheral logic pll. this allows the microprocessor and the peripheral logic block to operate at different frequencies, while maintaining a synchronous bus interface. the interface uses a 64- or 32-bit data bus (depending on memory data bus width) and a 32-bit address bus along with control signals that enable the interface between the processor and peripheral logic to be optimized for performance. pci accesses to the pc8240?s memory space are passed to the processor bus for snooping purposes when snoop mode is enabled. the pc8240?s features serve a variety of embedded applications. in this way, the 603e core and peripheral logic remain general-purpose. the pc8240 can be used as either a pci host or an agent controller. screening/quality/packaging this product is manufactured in full compliance with: upscreening based upon atmel standards industrial temperature range (t c =-40c,t c =+110 c) (t c =-40c,t c =+125 c): zd3 suffix core power supply: 2.5 5 % v (l-spec for 200 mhz) i/o power supply: 3.0v to 3.6v 352 tape ball grid array (tbga) tp suffix tbga352 tape ball grid array integrated processor family pc8240 rev. 2149a?hirel?05/02
2 pc8240 2149a?hirel?05/02 general description block diagram the pc8240 integrated processor is comprised of a peripheral logic block and a 32-bit superscalar powerpc 603e core, as shown in figure 1. figure 1. block diagram peripheral logic instruction unit address translator dll fanout buffers pci arbiter message controller (i2o) i2c controller dma controller epic interrupt controller /timers pci bus interface unit data path ecc controller memory controller central control unit oscillator input five request/ grant pairs i2c 5 irqs/ 16 serial interrupts 603e processor core block peripheral logic block processor pll instruction mmu (64-bit) two-instruction fetch (64-bit) two-instruction dispatch peripheral logic pll sdram clocks pci clock in pci bus clocks data (64-bit) address (32-bit) data bus (32- or 64-bit) with 8-bit parity or ecc memory/rom/portx address and control 64-bit 32-bit pci interface branch processing unit (bpu) system register unit (sru) floating point unit (fpu) integer unit (iu) load/store unit (lsu) bus configuration registers data mmu 16-kbyte data cache 16-kbyte instruction cache additional features: ? jtag/cop interface power management pc8240
3 pc8240 2149a?hirel?05/02 pinout listing table 1 provides the pinout listing for the pc8240, 352 tbga package. table 1. pc8240 pinout listing signal name package pin number pin type power supply output driver type notes pci interface signals c/be [0 ? 3] a25 f23 k23 p25 i/o ovdd drv_pci (6)(15) devsel h26 i/o ovdd drv_pci (8)(15) frame j24 i/o ovdd drv_pci (8)(15) irdy k25 i/o ovdd drv_pci (8)(15) lock j26 input ovdd ? (8) ad[0 ? 31] c22 d22 b22 b23 d19 b24 a24 b26 a26 c26 d25 d26 e23 e25 e26 f24 l26 l25 m25 m26 n23 n25 n26 r26 r25 t26 t25 u23 u24 u26 u25 v25 i/o ovdd drv_pci (6)(15) par g25 i/o ovdd drv_pci (15) gnt [0 ? 3] v26 w23 w24 w25 output ovdd drv_pci (6)(15) gnt4 /da5 w26 output ovdd drv_pci (7)(15) req [0 ? 3] ab26 aa25 aa26 y25 input ovdd ? (6)(12) req4 /da4 y26 input ovdd ? (12) perr g26 i/o ovdd drv_pci (8)(15)(18) serr f26 i/o ovdd drv_pci (8)(15)(16) stop h25 i/o ovdd drv_pci (8)(15) trdy k26 i/o ovdd drv_pci (8)(15) inta ac26 output ovdd drv_pci (15)(16) idsel p26 input ovdd ? ? memory interface signals mdl[0 ? 31] ad17 ae17 ae15 af15 ac14 ae13 af13 af12 af11 af10 af9 ad8 af8 af7 af6 ae5 b1 a1 a3 a4 a5 a6 a7 d7 a8 b8 a10 d10 a12 b11 b12 a14 i/o gvdd drv_mem_data (5)(6)(13) mdh[0 ? 31] ac17 af16 ae16 ae14 af14 ac13 ae12 ae11 ae10 ae9 ae8 ac7 ae7 ae6 af5 ac5 e4 a2 b3 d4 b4 b5 d6 c6 b7 c9 a9 b10 a11 a13 b13 a15 i/o gvdd drv_mem_data (6)(13) cas /dqm[0 ? 7] ab1 ab2 k3 k2 ac1 ac2 k1 j1 output gvdd drv_mem_addr (6) ras/cs [0 ? 7] y4 aa3 aa4 ac4 m2 l2 m1 l1 output gvdd drv_mem_addr (6) foe h1 i/o gvdd drv_mem_addr (3)(4) rcs0 n4 i/o gvdd drv_mem_addr (3)(4) rcs1 n2 output gvdd drv_mem_addr ?
4 pc8240 2149a?hirel?05/02 sdma[11 ? 0] n1 r1 r2 t1 t2 u4 u2 u1 v1 v3 w1 w2 output gvdd drv_mem_addr (6)(14) sdma12/sdba1 p1 output gvdd drv_mem_addr (14) sdba0 p2 output gvdd drv_mem_addr ? par[0 ? 7] af3 ae3 g4 e2 ae4 af4 d2 c2 i/o gvdd drv_mem_addr (6)(13)(14) sdras ad1 output gvdd drv_mem_addr (3) sdcas ad2 output gvdd drv_mem_addr (3) cke h2 output gvdd drv_mem_addr (3)(4) we aa1 output gvdd drv_mem_addr ? as y1 output gvdd drv_mem_addr (3)(4) epic control signals irq_0/s_int c19 input ovdd ? ? irq_1/s_clk b21 i/o ovdd drv_pci ? irq_2/s_rst ac22 i/o ovdd drv_pci ? irq_3/s_frame ae24 i/o ovdd drv_pci ? irq_4/ l_int a23 i/o ovdd drv_pci ? two-wire interface control signals sda ae20 i/o ovdd drv_std (10)(16) scl af21 i/o ovdd drv_std (10)(16) clock out signals pci_clk[0 ? 3] ac25 ab25 ae26 af25 output gvdd drv_pci_clk (6) pci_clk4/da3 af26 output gvdd drv_pci_clk ? pci_sync_out ad25 output gvdd drv_pci_clk ? pci_sync_in ab23 input gvdd ? ? sdram_clk[0 ? 3] d1 g1 g2 e1 output gvdd drv_mem_addr (6) sdram_sync_out c1 output gvdd drv_mem_addr ? sdram_sync_in h3 input gvdd ? ? cko/da1 b15 output ovdd drv_std ? osc_in ad21 input ovdd ? ? miscellaneous signals hrst_ctrl a20 input ovdd ? ? hrst_cpu a19 input ovdd ? ? mcp a17 output ovdd drv_std (3)(4)(17) nmi d16 input ovdd ? ? smi a18 input ovdd ? (10) sreset b16 input ovdd ? (10) table 1. pc8240 pinout listing (continued) signal name package pin number pin type power supply output driver type notes
5 pc8240 2149a?hirel?05/02 tben b14 input ovdd ? (10) qack /da0 f2 output ovdd drv_std (3)(4) chkstop_in d14 input ovdd ? (10) maa[0 ? 2] af2 af1 ae1 output ? drv_mem_data (3)(4)(6) miv a16 output ovdd drv_std ? pmaa[0 ? 2] ad18 af18 ae19 output ovdd drv_std (3)(4)(6)(15) test/configuration signals pll_cfg[0 ? 4]/ da[10 ? 6] a22 b19 a21 b18 b17 input ovdd ? (4)(6) test [0 ? 1] ad22 b20 input ovdd ? (1)(6)(9) test2 y2 input ? ? (11) test3 af20 input ovdd ? (10) test4 ac18 i/o ovdd drv_std (10) tck af22 input ovdd ? (9)(12) tdi af23 input ovdd ? (9)(12) tdo ac21 output ovdd drv_pci ? tms ae22 input ovdd ? (9)(12) trst ae23 input ovdd ? (9)(12) power and ground signals gnd aa2 aa23 ac12 ac15 ac24 ac3 ac6 ac9 ad11 ad14 ad16 ad19 ad23 ad4 ae18 ae2 ae21 ae25 b2 b25b6b9c11c13c16c23c4c8 d12 d15 d18 d21 d24 d3 f25 f4 h24 j25 j4 l24 l3 m23 m4 n24 p3 r23r4t24t3v2v23w3 ground 52 terminals ??? lvdd ac20 ac23 d20 d23 g23 p23 y23 reference voltage 3.3v, 5.0v lvdd ? ? gvdd ab3 ab4 ac10 ac11 ac8 ad10 ad13 ad15 ad3 ad5 ad7 c10 c12 c3 c5 c7 d13 d5 d9 e3 g3 h4 k4 l4 n3 p4 r3 u3 v4 y3 power for memory drivers 2.5v, 3.3v gvdd ? ? ovdd ab24 ad20 ad24 c14 c20 c24 e24 g24 j23 k24 m24 p24 t23 y24 pci/stnd 3.3v ovdd ? ? vdd aa24 ac16 ac19 ad12 ad6 ad9 c15 c18 c21 d11 d8 f3 h23 j3 l23 m3 r24 t4 v24 w4 power for core 2.5v vdd ? ? lavdd d17 power for dll 2.5v lavdd ? ? table 1. pc8240 pinout listing (continued) signal name package pin number pin type power supply output driver type notes
6 pc8240 2149a?hirel?05/02 notes: 1. place pull-up resistors of 120 ? or less on the test [0 ? 1] pins. 2. treat these pins as no connects unless using debug address functionality. 3. this pin has an internal pull-up resistor which is enabled only when the pc8240 is in the reset state. the value of the inter- nal pull-up resistor is not guaranteed, but is sufficient to ensure that a "1" is read into configuration bits during reset. 4. this pin is a reset configuration pin. 5. dl[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the pc8240 is in the reset state. the value of the internal pull-up resistor is not guaranteed, but is sufficient to insure that a "1" is read into configuration bits during reset. 6. multi-pin signals such as ad[0 ? 31] or dl[0 ? 31] have their physical package pin numbers listed in order corresponding to the signal names. ex: ad0 is on pin c22, ad1 is on pin d22,... ad31 is on pin v25. 7. gnt4 is a reset configuration pin and has an internal pull-up resistor which is enabled only when the pc8240 is in the reset state. the value of the internal pull-up resistor is not guaranteed, but is sufficient to insure that a "1" is read into configuration bits during reset. 8. recommend a weak pull-up resistor (2 k ? ?10k ? )beplacedonthispcicontrolpintolvdd. 9. v ih and v il for these signals are the same as the pci v ih and v il entries in table 6, ?dc electrical specifications,? on page 16. 10. recommend a weak pull-up resistor (2 k ? ?10k ? )beplacedonthispintoovdd. 11. recommend a weak pull-up resistor (2 k ? ?10k ? )beplacedonthispintogvdd. 12. this pin has an internal pull-up resistor; the value of the internal pull-up resistor is not guaranteed, but is sufficient to prevent unused inputs from floating. 13. output valid specifications for this pin are memory interface mode dependent (registered or flow-through), see table 11, ?output ac timing specifications,? on page 22. 14. non-dram access output valid specification applies to this pin during non-dram accesses, see specification 12b3 in table 11, ?output ac timing specifications,? on page 22. 15. this pin is affected by programmable pci_hold_del parameter, see ?pci signal output hold timing? on page 23. 16. this pin is an open drain signal. 17. this pin can be programmed to be driven (default) or can be programmed to be open drain; see pmcr2 register description in the motorola pc8240 user?s manual for details. 18. this pin is a sustained tri-state pin as defined by the pci local bus specification. avdd c17 power for pll (cpu core logic) 2.5v avdd ? ? avdd2 af24 power for pll (peripheral logic) 2.5v avdd2 ? ? manufacturing pins da2 c25 i/o ovdd drv_pci (2) da[11 ? 13] ad26 af17 af19 i/o ovdd drv_pci (2)(6) da[14 ? 15] f1 j2 i/o gvdd drv_mem_addr (2)(6) table 1. pc8240 pinout listing (continued) signal name package pin number pin type power supply output driver type notes
7 pc8240 2149a?hirel?05/02 detailed specification scope this drawing describes the specific requirements for the pc8240 processor, in compli- ance with atmel standard screening. applicable documents 1. mil-std-883: test methods and procedures for electronics. 2. mil-prf-38535: general specifications for microcircuits. requirements general the microcircuits are in accordance with the applicable documents and as specified herein. design and construction terminal connections the terminal connections are shown in table 1, ?pc8240 pinout listing,? on page 3. absolute maximum ratings notes: 1. functional and tested operating conditions are given in table 3. absolute maximum ratings are stress ratings only and functional operation at the maximums is not guar- anteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. pci inputs with lvdd = 5v 5% v dc may be correspondingly stressed at voltages exceeding lvdd + 0.5v dc. table 2. absolute maximum ratings symbol characteristic (1) value unit vdd supply voltage ? cpu core and peripheral logic -0.3 to 2.75 v gvdd supply voltage ? memory bus drivers -0.3 to 3.6 v ovdd supply voltage ? pci and standard i/o buffers -0.3 to 3.6 v avdd/avdd2/lavdd supply voltage ? plls and dll -0.3 to 2.75 v v in supply voltage ? pci reference -0.3 to 3.6 v lvdd input voltage (2) -0.3 to 5.4 v t stg storage temperature range -55 to 150 c
8 pc8240 2149a?hirel?05/02 recommended operating conditions notes: 1. these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. 2. pci pins are designed to withstand lvdd + 0.5v dc when lvdd is connected to a 5.0v dc power supply. 3. pci pins are designed to withstand lvdd + 0.5v dc when lvdd is connected to a 3.3v dc power supply. 4. caution: input voltage (v in ) must not be greater than the supply voltage (vdd/avdd/avdd2/lavdd) by more than 2.5v at all times including during power-on reset. 5. caution: ovdd must not exceed vdd/avdd/avdd2/lavdd by more than 1.8v at any time including during power-on reset. 6. caution: vdd/avdd/avdd2/lavdd must not exceed ovdd by more than 0.6v at any time including during power-on reset. 7. caution: gvdd must not exceed vdd/avdd/avdd2/lavdd by more than 1.8v at any time including during power-on reset. 8. caution: lvdd must not exceed vdd/avdd/avdd2/lavdd by more than 5.4v at any time including during power-on reset. 9. caution: lvdd must not exceed ovdd by more than 3.6v at any time including during power-on reset. table 3. recommended operating conditions symbol characteristic (1) recommended value unit notes vdd supply voltage 2.5 5 % v (5) ovdd i/o buffer supply for pci and standard 3.3 0.3 v (5) gvdd supply voltages for memory bus drivers 3.3 5 % v (7) 2.55% v (7) avdd pll supply voltage ? cpu core logic 2.5 5 % v (5) avdd2 pll supply voltage ? peripheral logic 2.55% v (6) lavdd dll supply voltage 2.55% v (6) lvdd pci reference 5 5 % v (8)(9) 3.3 0.3 v (8)(9) v in input voltage pci inputs 0 to 3.6 or 5.75 v (2)(3) all other inputs 0 to 3.6 v (4) t c operating temperature -40 to 125 c
9 pc8240 2149a?hirel?05/02 figure 2. supply voltage sequencing and separation cautions notes: 1. numbers associated with waveform separations correspond to caution numbers listed in table 3, ?recommended operat- ing conditions,? on page 8. 2. refer to ?power supply voltage sequencing? on page 35 for additional information. 3. refer to table 9 on page 18 for additional information on pll relock and reset signal assertion timing requirements. 4. refer to table 10 on page 20 for additional information on reset configuration pin setup timing requirements. 5. hrst_cpu/hrst_ctrl must transition from a logic 0 to a logic 1 in less than one sdram_sync_in clock cycle for the devicetobeinthenon-resetstate. ovdd/gvdd/(lvdd@3.3v ----) vdd/avdd/avdd2/lavdd lvdd at 5v time 3.3v 5v 2.5v 0 7 10 9 9 10 6.8 dc power supply voltage voltage regulator delay (2) reset configuration pins hrst_cpu & hrst_ctrl asserted 255 external memory clock cycles (3) 9 external memory clock cycles setup time (4) hrst_cpu & hrst_ctrl vdd stable (1) vm = 1.4v maximum rise time must be less than one external memory clock cycle (5) 100 ms pll relock time (3) power supply ramp up (2)
10 pc8240 2149a?hirel?05/02 figure 3 shows the undershoot and overshoot voltage of the memory interface of the pc8240. figure 3. overshoot/undershoot voltage thermal information thermal characteristics thermal management information this section provides thermal management information for the tape ball grid array (tbga) package for air-cooled applications. proper thermal control design is primarily dependent upon the system-level design, the heat sink, airflow and thermal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods-adhesive, spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly; see figure 4. figure 4. package exploded cross-sectional view with several heat sink options gnd gnd 0.3v gnd 1.0v not to exceed 10% of tsdram_clk gvdd gvdd + 5% 4v vih vil table 4. package thermal characteristics symbol characteristic min unit jc die junction-to-case thermal resistance 1.8 c/w jb die junction-to-board thermal resistance 4.8 c/w adhesive or thermal interface material die heat sink tbga package heat sink clip printed-circuit board option
11 pc8240 2149a?hirel?05/02 figure 5 depicts the die junction-to-ambient thermal resistance for four typical cases: 1. a heat sink is not attached to the tbga package and there exists high board- level thermal loading of adjacent components. 2. a heat sink is not attached to the tbga package and there exists low board- level thermal loading of adjacent components. 3. a heat sink (e.g. chipcoolers #hts255-p) is attached to the tbga package and there exists high board-level thermal loading of adjacent components. 4. a heat sink (e.g. chipcoolers #hts255-p) is attached to the tbga package and there exists low board-level thermal loading of adjacent components. figure 5. die junction-to-ambient resistance die junction ? to ? ambient thermal resistance (* ring* c/ w) airflow velocity (m/s) no heat sink and high thermal board ? level loading of adjacent components no heat sink and low thermal board ? level loading of adjacent components attached heat sink and high thermal board ? level loading of adjacent components attached heat sink and low thermal board ? level loading of adjacent components 2 0 0.5 1 1.5 2 2.5 4 6 8 10 12 14 16 18
12 pc8240 2149a?hirel?05/02 the board designer can choose between several types of heat sinks to place on the pc8240. there are several commercially-available heat sinks for the pc8240 provided by the following vendors: ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. internal package conduction resistance for the tbga, cavity down, packaging technology, shown in figure 4 on page 10, the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case thermal resistance, the die junction-to-ball thermal resistance. figure 6 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. figure 6. c4 package with heat sink mounted to a printed-circuit board for this cavity-down, wire-bond tbga package, heat generated on the active side of the chip is conducted through the silicon, the die attach and package spreader, then through the heat sink attach material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection. chip coolers inc. 333 strawberry field rd. warwick, ri 02887-6979 800-227-0254 (usa/canada) 401-739-7600 internet: www.chipcoolers.com international electronic research corporation (ierc) 135 w. magnolia blvd. burbank, ca 91502 818-842-7277 internet: www.ctscorp.com thermalloy 2021 w. valley view lane dallas, tx 75234-8993 972-243-4321 internet: www.thermalloy.com wakefield engineering 100 cummings center, suite 157h beverly, ma 01915 781-406-3000 internet: www.wakefield.com aavid engineering 250 apache trail terrell, tx 75160 972-551-7330 internet: www.aavid.com external resistance external re sistance internal resistance (note the internal versus external package resistance) radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package
13 pc8240 2149a?hirel?05/02 adhesives and thermal interface materials a thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal contact resistance. for those applications where the heat sink is attached by spring clip mechanism, figure 7 shows the thermal performance of three thinsheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure. as shown, the perfor- mance of these thermal interface materials improves with increasing contact pressure. the use of thermal grease significantly reduces the interface thermal resistance. that is, the bare joint results in a thermal resistance approximately 7 times greater than the ther- mal grease joint. heat sinks are attached to the package by means of a spring clip to holes in the printed- circuit board (see figure 6). therefore, the synthetic grease offers the best thermal per- formance, considering the low interface pressure. of course, the selection of any thermal interface material depends on many factors, thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, etc. figure 7. thermal performance of select thermal interface material 0 0 1020304050607080 0.5 1 1.5 2 silicone sheet (0.006 inch) bare joint floroether oil sheet (0.007 inch) graphite/oil sheet (0.005 inch) synthetic grease contact pressure (psi) specific thermal resistance (kin2/w)
14 pc8240 2149a?hirel?05/02 the board designer can choose between several types of thermal interface. heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. there are several commercially-available thermal interfaces and adhesive materials provided by the fol- lowing vendors: heat sink selection example for preliminary heat sink sizing, the die-junction temperature can be expressed as follows: t j =t a +t r +( jc + int + sa )xp d where: t j is the die-junction temperature. t a is the inlet cabinet ambient temperature. t r is the air temperature rise within the computer cabinet. jc is the junction-to-case thermal resistance. int is the adhesive or interface material thermal resistance. sa is the heat sink base-to-ambient thermal resistance. p d is the power dissipated by the device. during operation the die-junction temperatures (t j ) should be maintained less than the value specified in table. the temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the electronic cabinet. an electronic cabinet inlet-air temperature (t a )mayrangefrom30to 40 c. the air temperature rise within a cabinet (t r ) may be in the range of 5 to 10 c. the thermal resistance of the thermal interface material ( int ) is typically about 1 c/w. assuming a t a of 30 c, a t r of 5 c, a tbga package jc = 1.8, and a power consump- tion (p d ) of 5.0 watts, the following expression for t j is obtained: die-junction temperature: t j =30 c+5 c+(1.8 c/w + 1.0 c/w + sa )x5.0w for preliminary heat sink sizing, the heat sink base-to-ambient thermal resistance is needed from the heat sink manufacturer. though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can ade- quately describe three-dimensional heat flow. dow-corning corporation dow-corning electronic materials po box 0997 midland, mi 48686-0997 800-248-2481 internet: www.dow.com chomerics, inc. 77 dragon court woburn, ma 01888-4014 781-935-4850 internet: www.chomerics.com thermagon inc. 3256 west 25th street cleveland, oh 44109-1668 888-246-9050 internet: www.thermagon.com loctite corporation 1001 trout brook crossing rocky hill, ct 06067-3910 860-571-5100 internet: www.loctite.com
15 pc8240 2149a?hirel?05/02 the final die-junction operating temperature, is not only a function of the component- level thermal resistance, but the system-level design and its operating conditions. in addition to the component?s power consumption, a number of factors affect the final operating die-junction temperature-airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, etc. due to the complexity and the many variations of system-level boundary conditions for today?s microelectronic equipment, the combined effects of the heat transfer mecha- nisms (radiation, convection and conduction) may vary widely. for these reasons, we recommend using conjugate heat transfer models for the board, as well as, system-level designs. to expedite system-level thermal analysis, several ?compact? thermal-package models are available within flotherm ? . these are available upon request. power consideration table 5 provides preliminary power consumption data for the pc8240. at recommended operating conditions (see table 3 on page 8) with gvdd = 3.3v 5% andlvdd=3.3v5% notes: 1. the values include vdd, avdd, avdd2, and lvdd but do not include i/o supply power, see ?power supply sizing? on page 36 for information on ovdd and gvdd supply power. 2. maximum ? fp power is measured at vdd = 2.625v with dynamic power management enabled while running an entirely cacheresident, looping, floating point multiplication instruction. 3. maximum ? int power is measured at vdd = 2.625v with dynamic power management enabled while running entirely cache-resident, looping, integer instructions. 4. power saving mode maximums are measured at vdd = 2.625v while the device is in doze, nap, or sleep mode. 5. typical power is measured at vdd = avdd = 2.5v, ovdd = 3.3v where a nominal fp value, a nominal int value, and a value where there is a continuous flush of cache lines with alternating ones and zeroes on 64-bit boundaries to local mem- ory are averaged. 6. power saving mode data measured with only two pci_clks and two sdram_clks enabled. 7. the typical minimum i/o power values were results of the pc8240 performing cache resident integer operations at the slow- est frequency combination of 33:66:166 (pci:mem:cpu) mhz. 8. the typical maximum ovdd value resulted from the pc8240 operating at the fastest frequency combination of 66:100:200 (pci:mem:cpu) mhz and performing continuous flushes of cache lines with alternating ones and zeroes to pci memory. table 5. preliminary power consumption mode pci bus clock/memory bus clock cpu clock frequency (mhz) unit notes 33/66/166 33/66/200 33/100/200 66/100/200 typical 2.5 2.8 3.0 3.0 w (1)(5) max ? fp 3.0 3.4 3.6 3.6 w (1)(2) max ? int 2.7 3.0 3.3 3.4 w (1)(3) doze 1.8 2.0 2.2 2.2 w (1)(4)(6) nap 700 700 900 900 mw (1)(4)(6) sleep 500 500 500 800 mw (1)(4)(6) i/o power supplies mode minimum maximum unit notes typ ? ovdd 200 600 mw (7)(8) typ ? gvdd 300 900 mw (7)(9)
16 pc8240 2149a?hirel?05/02 9. the typical maximum gvdd value resulted from the pc8240 operating at the fastest frequency combination of 66:100:200 (pci:mem:cpu) mhz and performing continuous flushes of cache lines with alternating ones and zeroes on 64-bit bound- aries to local memory. note: to calculate the power consumption at low temperature (-55c), use a 1.25 factor. marking the document where markings are defined is identified in the related reference docu- ments. each microcircuit is legible and permanently marked with the following information as minimum: atmel logo, manufacturer?s part number,date-code of inspection lot, esd identifier if available, country of manufacturing. electrical characteristics static characteristics table 6 provides the dc electrical characteristics for the pc8240. at recommended operating conditions (see table 3 on page 8) notes: 1. see table 1 on page 3 for pins with internal pull-up resistors. 2. capacitance is periodically sampled rather than 100% tested. table 6. dc electrical specifications characteristics (1) conditions (4) symbol value unit min max input high voltage pci only v ih 0.5*ovdd lvdd v input low voltage pci only v il ?0.3*ovddv input high voltage all other pins (gvdd = 3.3v) v ih 2.0 3.3 v input high voltage all other pins (gvdd = 2.5v) v ih 1.8 2.5 v input low voltage all inputs except osc_in v il gnd 0.8 v pci_sync_in input high voltage cv ih 0.5*ovdd ? v pci_sync_in input low voltage cv il gnd 0.3*ovdd v input leakage current (5) for pins using drv_pci driver 0.5v v in 2.7v at lvdd = 4.75 i l ?70a input leakage current (5) for pins using drv_pci driver 0.5v v in 5.5v at lvdd = 5.5 i l ?tbda input leakage current (5) all others lvdd = 3.6v gvdd = 3.465 i l ?10a output high voltage i oh = n/a (gvdd = 3.3v) (3) v oh 2.4 ? v output low voltage i ol =n/a(gvdd=3.3v) (3) v ol ?0.4v output high voltage i oh = n/a (gvdd = 2.5v) (3) v oh 1.85 ? v output low voltage i ol =n/a(gvdd=2.5v) (3) v ol ?0.6v capacitance (2) v in =0v,f=1mhz c in ?7.0pf
17 pc8240 2149a?hirel?05/02 3. see table 7 on page 17 for the typical drive capability of a specific signal pin based upon the type of output driver associ- ated with that pin as listed in. 4. these specifications are for the default driver strengths indicated in table. 5. leakage current is measured on input pins and on output pins in the high impedance state. the leakage current is mea- sured for nominal ovdd/lvdd and vdd or both ovdd/lvdd and vdd must vary in the same direction. table 7 provides information on the characteristics of the output drivers referenced in. the values are from the pc8240 ibis model (v1.0) and are not tested, for additional detailed information see the complete ibis model listing at http://www.mot.com/sps/powerpc/ teksupport/tools/ibis/kahlua_1.ibs.txt notes: 1. for drv_pci, i oh read from the listing in the pull-up mode, i(min) column, at the 0.33v label by interpolating between the 0.3v and 0.4v table entries? current values which correspond to the pci v oh = 2.97 = 0.9*lvdd (lvdd = 3.3v) where table entry voltage = lvdd - pci v oh . 2. for all others with ovdd or gvdd = 3.3v, i oh read from the listing in the pull-up mode, i(min) column, at the 0.9v table entry which corresponds to the v oh = 2.4v where table entry voltage = o/gvdd - pci v oh . 3. for gvdd = 2.5v, i oh read from the listing in the pull-up mode, i(min) column, at the tbdv table entry which corresponds to the v oh = tbd v where table entry voltage = gvdd - v oh . 4. for drv_pci, i ol read from the listing in the pull-down mode, i(max) column, at 0.33v = pci v ol = 0.1*lvdd (lvdd = 3.3v) by interpolating between the 0.3v and 0.4v table entries. 5. for all others with ovdd or gvdd = 3.3v, i ol read from the listing in the pull-down mode, i(max) column, at the 0.4v table entry. 6. for gvdd = 2.5v, i ol read from the listing in the pull-down mode, i(max) column, at the tbdv table entry. table 7. drive capability of pc8240 output pins driver type programmable output impedance (ohms) supply voltage (v) i oh i ol unit notes drv_std 20 ovdd = 3.3 tbd tbd ma (2)(5) 40 (default) ovdd = 3.3 tbd tbd ma (2)(5) drv_pci 25 lvdd = 3.3 11.0 20.6 ma (1)(4) lvdd = 5.0 5.6 10.3 ma (1)(4) 50 (default) lvdd = 3.3 5.6 10.3 ma (1)(4) lvdd = 5.0 5.6 10.3 ma (1)(4) drv_mem_addr drv_pci_clk 8 (default) gvdd = 2.5 tbd tbd ma (3)(6) gvdd = 3.3 89.0 73.3 ma (2)(5) 13.3 gvdd = 2.5 tbd tbd ma (3)(6) gvdd = 3.3 55.9 46.4 ma (2)(5) 20 gvdd = 2.5 tbd tbd ma (3)(6) gvdd = 3.3 36.7 30.0 ma (2)(5) 40 gvdd = 2.5 tbd tbd ma (3)(6) gvdd = 3.3 tbd tbd ma (2)(5) drv_mem_data 20 (default) gvdd = 2.5 tbd tbd ma (3)(6) gvdd = 3.3 36.7 30.0 ma (2)(5) 40 gvdd = 2.5 tbd tbd ma (3)(6) gvdd = 3.3 18.7 15.0 ma (2)(5)
18 pc8240 2149a?hirel?05/02 dynamic electrical characteristics this section provides the ac electrical characteristics for the pc8240. after fabrication, functional parts are sorted by maximum processor core frequency as shown in table 9, ?clock ac timing specifications,? on page 18 and tested for conformance to the ac specifications for that frequency. the processor core frequency is determined by the bus (pci_sync_in) clock frequency and the settings of the pll_cfg[0-4] signals. parts are sold by maximum processor core frequency; see ?ordering information? on page 41. table 8 provides the operating frequency information for the pc8240. at recommended operating conditions (see table 3 on page 8) with gvdd = 3.3v 5% andlvdd=3.3v5% note: 1. caution: the pci_sync_in frequency and pll_cfg[0 ? 4] settings must be chosen such that the resulting peripheral logic/memory bus frequency, cpu (core) fre- quency, and pll (vco) frequencies do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0 ? 4] signal description in ?pll configuration? on page 34 for valid pll_cfg[0 ? 4] settings and pci_sync_in frequencies. clock ac specifications table 9 provides the clock ac timing specifications as defined in section. at recommended operating conditions (see table 3 on page 8) with gvdd = 3.3v 5% andlvdd=3.3v5% table 8. operating frequency characteristic (1) 200 mhz unit min max processor frequency (cpu) 100 200 mhz memory bus frequency 25 - 100 mhz pci input frequency 25 - 66 mhz table 9. clock ac timing specifications num characteristics and conditions (1) min max unit notes 1a frequency of operation (pci_sync_in) 25 66 mhz 1b pci_sync_in cycle time 40 15 ns 2, 3 pci_sync_in rise and fall times ? 2.0 ns (2) 4 pci_sync_in duty cycle measured at 1.4v 40 60 % 5a pci_sync_in pulse width high measured at 1.4v 6 9 ns (3) 5b pci_sync_in pulse width low measured at 1.4v 6 9 ns (3) 7 pci_sync_in short term jitter (cycle to cycle) ? < 500 ps 8a pci_clk[0 ? 4] skew (pin to pin) 0 500 ps 8b sdram_clk[0 ? 3] skew (pin to pin) tbd tbd ps (8) 10 internal pll relock time ? 100 s (3)(4)(6) 15 dll lock range with dll_extend = 0 disabled (default) 0 (nt clk -t loop -t fix0 )7 ns (7) 16 dll lock range with dll_extend = 1 enabled 0 (nt clk -t clk /2 - t loop -tf ix0 )7 ns (7) 17 frequency of operation (osc_in) 25 66 mhz
19 pc8240 2149a?hirel?05/02 notes: 1. these specifications are for the default driver strengths indicated in table 7 on page 17. 2. rise and fall times for the pci_sync_in input are measured from 0.4 to 2.4v. 3. specification value at maximum frequency of operation. 4. relock time is guaranteed by design and characterization. relock time is not tested. 5. rise and fall times for the osc_in input is guaranteed by design and characterization. osc_in input rise and fall times are not tested. 6. relock timing is guaranteed by design. pll-relock time is the maximum amount of time required for pll lock after a stable vdd and pci_sync_in are reached during the reset sequence. this specification also applies when the pll has been dis- abled and subsequently re-enabled during sleep mode. also note that hrst_cpu/hrst_ctrl must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the reset sequence. 7. dll_extend is bit 7 of the pmc2 register <72>. n is a non-zero integer (1, 2, 3, ...). t clk is the period of one sdram_sync_out clock cycle in ns. t loop is the propagation delay of the dll synchronization feedback loop (pc board runner) from sdram_sync_out to sdram_sync_in in ns; 6.25 inches of loop length (unloaded pc board runner) cor- responds to approximately 1 ns of delay. t fix0 is a fixed delay inherent in the design when the dll is at tap point 0 and the dll is contributing no delay; t fix0 equals approximately 3 ns. see figure 9 on page 20 for dll locking ranges. 8. pin to pin skew includes quantifying the additional amount of clock skew (or jitter) from the dll besides any intentional skew added to the clocking signals from the variable length dll synchronization feedback loop, i.e. the amount of variance between the internal sys-logic_clk and the sdram_sync_in signal after the dll is locked. while pin to pin skew between sdram_clks can be measured, the relationship between the internal sys-logic_clk and the external sdram_sync_in cannot be measured and is guaranteed by design. figure 8. pci_sync-in input clock timing diagram 18 osc_in cycle time 40 15 ns 19 osc_in rise and fall times ? 5 ns (5) 20 osc_in duty cycle measured at 1.4v 40 60 % 21 osc_in frequency stability ? 100 ppm 22 osc_in v ih (loaded) tbd v 23 osc_in v il (loaded) ? tbd v table 9. clock ac timing specifications (continued) num characteristics and conditions (1) min max unit notes 1 23 5a 5b vm vm vm cvil cvih vm = midpoint voltage (1.4v) pci_sync_in
20 pc8240 2149a?hirel?05/02 figure 9. dll locking range loop delay vs. frequency of operation input ac timing specifications table 10 provides the input ac timing specifications. see figure 10 on page 21 and fig- ure11onpage21. at recommended operating conditions (see table 3 on page 8) with gvdd = 3.3v 5% andlvdd=3.3v5% notes: 1. all memory and related interface input signal specifications are measured from the ttl level (0.8 or 2.0v) of the signal in question to the v m = 1.4v of the rising edge of the memory bus clock, sdram_sync_in. sdram_sync_in is the same as pci_sync_in in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of pci_sync_in). see figure 10 on page 21. tloop propagation delay time in nanoseconds dll will lock dll not guaranteed to lock n = 1 dll_extend = 0 n = 2 dll_extend = 1 n = 2 dll_extend = 0 n = 1 dll_extend = 1 0 ns 5 ns 10 ns 15 ns 100 mhz 10 ns 50 mhz 20 ns 33 mhz 30 ns 25 mhz 40 ns tclk sdram_ sync_ out period and frequency table 10. input ac timing specifications num characteristics min max unit notes 10a pci input signals valid to pci_sync_in (input setup) 2.0 ? ns (2)(3) 10b1 memory control and data input signals in flow through mode valid to sdram_sync_in (input setup) 4.0 ? ns (1)(3) 10b2 memory control and data input signals in registered mode valid to sdram_sync_in (input setup) tbd ? ns (1)(3) 10c epic, misc. debug input signals valid to sdram_sync_in (input setup) tbd ? ns (1)(3) 10d two-wire interface input signals valid to sdram_sync_in (input setup) tbd ? ns (1)(3) 10e mode select inputs valid to hrst_cpu/hrst_ctrl (input setup) 9*t clk ?ns (1)(3)(5) 11a pci_sync_in (sdram_sync_in) to inputs invalid (input hold) 1.0 ? ns (1)(2)(3) 11b hrst_cpu /hrst_ctrl to mode select inputs invalid (input hold) tbd ? ns (1)(3)(5)
21 pc8240 2149a?hirel?05/02 2. all pci signals are measured from ovdd/2 of the rising edge of pci_sync_in to 0.4*ovdd of the signal in question for 3.3v pci signaling levels. see figure 11. 3. input timings are measured at the pin. 4. t clk is the time of one sdram_sync_in clock cycle. 5. all mode select input signals specifications are measured from the ttl level (0.8 or 2.0v) of the signal in question to the v m = 1.4v of the rising edge of the hrst_cpu/hrst_ctrl signal. see figure 12. figure 10. input ? output timing diagram referenced to sdram_sync_in figure 11. input ? output timing diagram referenced to pci_sync_in figure 12. input timing diagram for mode select signals 11a vm vm = midpoint voltage (1.4v) memory 10b-d pci_sync_in inputs/outputs 13b 14b vm vm sdram_sync_in shown in 2:1 mode input timing output timing 12b-d 2.0v 0.8v 0.8v 2.0v ovdd/2 10a 11a pci_sync_in pci 12a 13a 14a ovdd/2 ovdd/2 0.4*ovdd 0.615*ovdd 0.285*ovdd input timing output timing inputs/outputs vm vm = midpoint voltage (1.4v) 11b mode pins 10e hrst_cpu/hrst_ctrl 2.0v 0.8v
22 pc8240 2149a?hirel?05/02 output ac timing specification table 11 provides the processor bus ac timing specifications for the pc8240. see fig- ure10onpage21andfigure11onpage21. at recommended operating conditions (see table 3 on page 8) with gvdd = 3.3v 5% andlvdd=3.3v5% notes: 1. all memory and related interface output signal specifications are specified from the v m = 1.4v of the rising edge of the mem- ory bus clock, sdram_sync_in to the ttl level (0.8 or 2.0v) of the signal in question. sdram_sync_in is the same as pci_sync_in in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of pci_sync_in). see figure 10 on page 21. 2. all pci signals are measured from ovdd/2 of the rising edge of pci_sync_in to 0.285*ovdd or 0.615*ovdd of the signal in question for 3.3v pci signaling levels. see figure 11 on page 21. 3. all output timings assume a purely resistive 50 ? load (see figure 13 on page 23). output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 4. pci bussed signals are composed of the following signals: lock , irdy ,c/be [0 ? 3], par, trdy ,frame ,stop , devsel , perr , serr , ad[0 ? 31], req [4?0],gnt [4 ? 0], idsel ,inta . 5. pci hold times can be varied, see ?pci signal output hold timing? on page 23 for information on programmable pci output hold times. the values shown for item 13a are for pci compliance. 6. these specifications are for the default driver strengths indicated in table 7 on page 17. table 11. output ac timing specifications num characteristics (3)(6) min max unit notes 12a pci_sync_in to output valid, 66 mhz pci, with mcp pulled-down to logic 0 state. see figure 14. ?6.0ns (2)(4) pci_sync_in to output valid, 33 mhz pci, with mcp in the default logic 1 state. see figure 14. ?8.0ns (2)(4) 12b1 sdram_sync_in to output valid (for memory control and data signals accessing dram in flow through mode) ?7.0ns (1) 12b2 sdram_sync_in to output valid (for memory control and data signals accessing dram in registered mode) ?tbdns (1) 12b3 sdram_sync_in to output valid (for memory control and data signals accessing non-dram) ?tbdns (1) 12c sdram_sync_in to output valid (for all others) ? 7.0 ns (1) 12d sdram_sync_in to output valid (for two-wire interface) ? tbd ns (1) 13a output hold, 66 mhz pci, with mcp and cke pulled-down to logic 0 states. see table 12. 0.5 ? ns (2)(4)(5) output hold, 33 mhz pci, with mcp in the default logic 1 state and cke pulled-down to logic 0 state. see table 12. 2.0 ? ns (2)(4)(5) 13b output hold (for all others) 0 ? ns (1) 14a pci_sync_in to output high impedance (for pci) ? tbd ns (2)(4) 14b sdram_sync_in to output high impedance (for all others) ? tbd ns (1)
23 pc8240 2149a?hirel?05/02 figure 13. actestloadforthepc8240 pci signal output hold timing in order to meet minimum output hold specifications relative to pci_sync_in for both 33 mhz and 66 mhz pci systems, the pc8240 has a programmable output hold delay for pci signals. the initial value of the output hold delay is determined by the values on the mcp and cke reset configuration signals. further output hold delay values are available by programming the pci_hold_del value of the pmcr2 configuration register. table 12 describes the bit values for the pci_hold_del values in pmcr2. output z0 = 50 ? ovdd/2 rl = 50 ? pin output measurements are made at the device pin table 12. power management configuration register 2-0x72 bit name reset value description 6?4 pci_hold_del xx0 pci output hold delay values relative to pci_sync_in. the initial values of bits 6 and 5 are determined by the reset configuration pins mcp and cke, respectively. as these two pins have internal pull-up resistors, the default value after reset is 0b110. while the minimum hold times are guaranteed at shown values, changes in the actual hold time can be made by incrementing or decrementing the value in these bit fields of this register via software or hardware configuration. the increment is in approximately 400 picosecond steps. lowering the value in the three bit field decreases the amount of output hold available. 000 66 mhz pci. pull-down mcp configuration pin with a 2k or less value resistor. this setting guarantees the minimum output hold, item 13a, and the maximum output valid, item 12a, times as specified in figure 11 are metfora66mhzpcisystem.seefigure14onpage24. 001 010 011 100 33 mhz pci. this setting guarantees the minimum output hold, item 13a, and the maximum output valid, item 12a, times as specified in figure 11 are met for a 33 mhz pci system. see figure 14 on page 24. 101 110 (default if reset configuration pins left unconnected) 111
24 pc8240 2149a?hirel?05/02 figure 14. pci_hold_del affect on output valid and hold time two-wire interface ac timing specifications table 13 provides the two-wire interface input ac timing specifications for the pc8240. at recommended operating conditions (see table 3 on page 8) with gvdd = 3.3v 5% andlvdd=3.3v5% pci_sync_in pci inputs/outputs 33 mhz pci 12a, 8 ns for 33 mhz pci pci_hold_del = 100 12a, 6 ns for 66 mhz pci pci_hold_del = 000 13a, 2 ns for 33 mhz pci pci_hold_del = 100 13a, 1 ns for 66 mhz pci pci_hold_del = 000 output valid output hold diagram not to scale as pci_hold_del values decrease as pci_hold_del values increase pci inputs and outputs pci inputs/outputs 66 mhz pci 0vdd 2 0vdd 2 table 13. two-wire interface input ac timing specifications num characteristics min max unit notes 1 start condition hold time 4.0 ? clks (1)(2) 2 clock low period (the time before the pc8240 will drive scl low as a transmitting slave after detecting scl low as driven by an external master.) 8.0 + (16 x 2 fdr[4:2] )x(5- 4({fdr[5],fdr[1]} == b?10) - 3({fdr[5],fdr[1]} == b?11) - 2({fdr[5],fdr[1]} == b?00) - 1({fdr[5],fdr[1]} == b?01)) ?clks (1)(2)(4)(5) 3 scl/sda rise time (from 0.5v to 2.4v) ? 1 ms 4 data hold time 0 ? ns (2) 5 scl/sda fall time (from 2.4v to 0.5v) ? 1 ms
25 pc8240 2149a?hirel?05/02 notes: 1. units for these specifications are in sdram_clk units. 2. the actual values depend on the setting of the digital filter frequency sampling rate (dffsr) bits in the frequency divider register i2cfdr. therefore, the noted timings in the above table are all relative to qualified signals. the qualified scl and sda are delayed signals from what is seen in real time on the two-wire interface bus. the qualified scl, sda signals are delayed by the sdram_clk clock times dffsr times 2 plus 1 sdram_clk clock. the resulting delay value is added to the value in the table (where this note is referenced). see figure 16 on page 27. 3. timing is relative to the sampling clock (not scl). 4. fdr[x] refers to the frequency divider register i2cfdr bit x. 5. input clock low and high periods in combination with the fdr value in the frequency divider register (i2cfdr) determine the maximum two-wire interface input frequency. see figure 16 on page 27. table 14 provides the two-wire interface frequency divider register (i2cfdr) informa- tion for the pc8240. at recommended operating conditions (see table 3 on page 8) with gvdd = 3.3v 5% and lvdd = 3.3v 5% 6 clock high period (time needed to either receive a data bit or generate a start or stop.) 5.0 ? clks (1)(2)(5) 7 data setup time 3.0 ? ns (3) 8 start condition setup time (for repeated start condition only) 4.0 ? clks (1)(2) 9 stop condition setup time 4.0 ? clks (1)(2) table 13. two-wire interface input ac timing specifications (continued) num characteristics min max unit notes table 14. pc8240 maximum two-wire interface input frequency fdr hex (2) divider (dec) (2) max two-wire interface input frequency (1) sdram_clk at 25 mhz sdram_clk at 33 mhz sdram_clk at 50 mhz sdram_clk at 100 mhz 20, 21 160, 192 862 1.13 mhz 1.72 mhz 3.44 mhz 22, 23, 24, 25 224, 256, 320, 384 555 733 1.11 mhz 2.22 mhz 0, 1 288, 320 409 540 819 1.63 mhz 2, 3, 26, 27, 28, 29 384, 448, 480, 512, 640, 768 324 428 649 1.29 mhz 4, 5 576, 640 229 302 458 917 6, 7, 2a, 2b, 2c, 2d 768, 896, 960, 1024, 1280, 1536 177 234 354 709 8, 9 1152, 1280 121 160 243 487 a, b, 2e, 2f, 30, 31 1536, 1792, 1920, 2048, 2560, 3072 92 122 185 371 c, d 2304, 2560 62 83 125 251 e, f, 32, 33, 34, 35 3072, 3584, 3840, 4096, 5120, 6144 47 62 95 190 10, 11 4608, 5120 32 42 64 128 12, 13, 36, 37, 38, 39 6144, 7168, 7680, 8192, 10240, 12288 24 31 48 96
26 pc8240 2149a?hirel?05/02 notes: 1. values are in khz unless otherwise specified. 2. fdr hex and divider (dec) values are listed in corresponding order. 3. multiple divider (dec) values will generate the same input frequency but each divider (dec) value will generate a unique output frequency as shown in table 15 on page 26. table 15 provides the two-wire interface output ac timing specifications for the pc8240. at recommended operating conditions (see table 3 on page 8) with gvdd = 3.3v 5% and lvdd = 3.3v 5% notes: 1. units for these specifications are in sdram_clk units. 2. the actual values depend on the setting of the digital filter frequency sampling rate (dffsr) bits in the frequency divider register i2cfdr. therefore, the noted timings in the above table are all relative to qualified signals. the qualified scl and sda are delayed signals from what is seen in real time on the two-wire interface bus. the qualified scl, sda signals are delayed by the sdram_clk clock times dffsr times 2 plus 1 sdram_clk clock. the resulting delay value is added to the value in the table (where this note is referenced). see figure 16 on page 27. 3. since scl and sda are open-drain type outputs, which the pc8240 can only drive low, the time required for scl or sda to reach a high level depends on external signal capacitance and pull-up resistor values. 14, 15 9216, 10240 16 21 32 64 16, 17, 3a, 3b, 3c, 3d 12288, 14336, 15360, 16384, 20480, 24576 12 16 24 48 18, 19 18432, 20480 8 10 16 32 1a, 1b, 3e, 3f 24576, 28672, 30720, 32768 681224 1c, 1d 36864, 40960 4 5 8 16 1e, 1f 49152, 61440 3 4 6 12 table 14. pc8240 maximum two-wire interface input frequency (continued) fdr hex (2) divider (dec) (2) max two-wire interface input frequency (1) sdram_clk at 25 mhz sdram_clk at 33 mhz sdram_clk at 50 mhz sdram_clk at 100 mhz table 15. two-wire interface output ac timing specifications num characteristics min max unit notes 1 start condition hold time (fdr[5] == 0) x (d fdr /16)/2n + (fdr[5] == 1) x (d fdr /16)/2m ?clks (1)(2)(5) 2 clock low period d fdr /2 ? clks (1)(2)(5) 3 scl/sda rise time (from 0.5v to 2.4v) ? ? ms (3) 4 data hold time 8.0 + (16 x 2 fdr[4:2] )x(5- 4({fdr[5],fdr[1]} == b?10) - 3({fdr[5],fdr[1]} == b?11) - 2({fdr[5],fdr[1]} == b?00) - 1({fdr[5],fdr[1]} == b?01)) ?clks (1)(2)(5) 5 scl/sda fall time (from 2.4v to 0.5v) < 5 ns (4) 6clockhightime d fdr /2 ? clks (1)(2)(5) 7 data setup time (pc8240 as a master only) (d fdr /2) - (output data hold time) ? clks (1)(5) 8 start condition setup time (for repeated start condition only) d fdr + (output start condition hold time) ?clks (1)(2)(5) 9 stop condition setup time 4.0 ? clks (1)(2)
27 pc8240 2149a?hirel?05/02 4. specified at a nominal 50 pf load. 5. d fdr is the decimal divider number indexed by fdr[5:0] value. refer to the two-wire interface interface chapter?s serial bit clock frequency divider selections table. fdr[x] refers to the frequency divider register i2cfdr bit x. n is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less than 16. m is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less than 9. figure 15. two-wire interface timing diagram i figure 16. two-wire interface timing diagram ii figure 17. two-wire interface timing diagram iii scl sda vm vm 6 2 1 4 scl sda vm vl vh 9 8 3 5 input data valid dffsr filter clk (1) sda 7 note 1: dffsr filter clock is the sdram_clk clock times dffsr value.
28 pc8240 2149a?hirel?05/02 figure 18. two-wire interface timing diagram iv (qualified signal) epic serial interrupt mode ac timing specifications table 16 provides the epic serial interrupt mode ac timing specifications for the pc8240. at recommended operating conditions (see table 3 on page 8) with gvdd = 3.3v 5% and lvdd = 3.3v 5% notes: 1. see the pc8240 user?s manual for a description of the epic interrupt control register (eicr) describing s_clk frequency programming. 2. s_rst, s_frame , and s_int shown in figure 19 and figure 20 depict timing relationships to sys_logic_clk and s_clk and do not describe functional relationships between s_rst, s_frame , and s_int. see the motorola?s pc8240 user?s manual for a complete description of the functional relationships between these signals. 3. the sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic pll; sys_logic_clk is the same as sdram_sync_in when the sdram_sync_out to sdram_sync_in feedback loop is implemented and the dll is locked. see motorola?s pc8240 user?s manual for a complete clocking description. scl/sdarealtime vm scl/sdaqualified vm delay (1) note 1: the delay is the local memory clock times dffsr times 2 plus 1 local memory clock. table 16. epic serial interrupt mode ac timing specifications num characteristics min max unit notes 1 s_clk frequency 1/14 sdram_sync_in 1/2 sdram_sync_in mhz (1) 2 s_clk duty cycle 40 60 % 3 s_clk output valid time ? tbd = x ns 4 output hold time 0 ? ns 5s_frame , s_rst output valid time ? 1 sys_logic_clk period + x ns (2) 6 s_int input setup time to s_clk 1 sys_logic_clk period + tbd ? ns (2) 7 s_int inputs invalid (hold time) to s_clk ?0ns (2)
29 pc8240 2149a?hirel?05/02 figure 19. epic serial interrupt mode output timing diagram figure 20. epic serial interrupt mode input timing diagram ieee 1149.1 (jtag) ac timing specifications table 17 provides the jtag ac timing specifications for the pc8240 while in the jtag operating mode. at recommended operating conditions (see table 3 on page 8) with gvdd = 3.3v 5% andlvdd=3.3v5% s_clk s_rst vm vm vm s_frame sys_logic_clk3 vm vm vm vm 4 3 5 4 6 s_clk s_int 7 vm table 17. jtag ac timing specifications (independent of pci_sync_in) num characteristics (4) min max unit notes tck frequency of operation 0 25 mhz 1 tck cycle time 40 ? ns 2 tck clock pulse width measured at 1.5v 20 ? ns 3 tck rise and fall times 0 3 ns 4 trst_ setup time to tck falling edge 10 ? ns (1) 5trst_asserttime 10 ? ns 6 input data setup time 5 ? ns (2) 7 input data hold time 15 ? ns (2) 8 tck to output data valid 0 30 ns (3) 9 tck to output high impedance 0 30 ns (3)
30 pc8240 2149a?hirel?05/02 notes: 1. trst is an asynchronous signal. the setup time is for test purposes only. 2. non-test (other than tdi and tms) signal input timing with respect to tck. 3. non-test (other than tdo) signal output timing with respect to tck. 4. timings are independent of the system clock (pci_sync_in). figure 21. jtag clock input timing diagram figure 22. jtag trst timing diagram figure 23. jtag boundary scan timing diagram 10 tms, tdi data setup time 5 ? ns 11 tms, tdi data hold time 15 ? ns 12 tck to tdo data valid 0 15 ns 13 tck to tdo high impedance 0 15 ns table 17. jtag ac timing specifications (independent of pci_sync_in) num characteristics (4) min max unit notes tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage 4 5 trst_ tck 9 8 67 tck data inputs input valid data output valid data data outputs data outputs
31 pc8240 2149a?hirel?05/02 figure 24. test access port timing diagram preparation for delivery packaging microcircuits are prepared for delivery in accordance with mil-prf-38535. certificate of compliance atmel offers a certificate of compliance with each shipment of parts, affirming the prod- ucts are in compliance either with mil-std-883 and guaranteeing the parameters not tested at temperature extremes for the entire temperature range. handling mos devices must be handled with certain precautions to avoid damage due to accu- mulation of static charge. input protection devices have been designed in the chip to minimize the effect of this static buildup. however, the following handling practices are recommended: devices should be handled on benches with conductive and grounded surfaces. ground test equipment, tools and operator. do not handle devices by the leads. store devices in conductive foam or carriers. avoid use of plastic, rubber or silk in mos areas. maintain relative humidity above 50% if practical. 13 12 10 11 tck tdi, tms input valid data output valid data tdo tdo
32 pc8240 2149a?hirel?05/02 package description package parameters the pc8240 uses a 35 mm x 35 mm, cavity down, 352 pin tape ball grid array (tbga) package. the package parameters are as provided in the following list. table 18. package parameters parameter package outline 35 mm x 35 mm interconnects 352 pitch 1.27 mm solder balls 63/37 sn/pb solder balls diameter 0.75 mm maximum module height 1.65 mm co-planarity specification 0.15 mm maximum force 6.0 lbs. total, uniformly distributed over package (8 grams/ball)
33 pc8240 2149a?hirel?05/02 mechanical dimensions figure 25 shows the top surface, side profile, and pinout of the pc8240, 352 tbga package. figure 25. pc8240 package dimensions and pinout assignments b a c - e - - f - 0.150 - t - t h g 25 23 21 19 17 15 13 11 9 7 5 3 1 a c e g j l n r u w aa ac ae 352x j d top view 26 24 22 20 18 16 14 12 10 8 6 4 2 b d f h k m p t v y ab ad af corner k l bottom view k 1. drawing not to scale. 2. all measurements are in millimeters (mm). notes: min max a 34.8 35.2 b 34.8 35.2 c 1.45 1.65 d 0.60 0.90 g 1.27 basic h 0.85 0.95 k 31.75 basic l 0.50 0.70
34 pc8240 2149a?hirel?05/02 pll configuration the pc8240?s internal plls are configured by the pll_cfg[0?4] signals. for a given pci_sync_in (pci bus) frequency, the pll configuration signals set both the periph- eral logic/memory bus pll (vco) frequency of operation for the pci-to-memory frequency multiplying and the 603e cpu pll (vco) frequency of operation for memory- to-cpu frequency multiplying. the pll configuration for the pc8240 is shown in table 19. notes: 1. caution: the pci_sync_in frequency and pll_cfg[0 ? 4] settings must be chosen such that the resulting peripheral logic/ memory bus frequency, cpu (core) frequency, and pll (vco) frequencies do not exceed their respective maximum or minimum operating frequencies shown in table. bold font numerical pairs indicate input range limit and limiting parameter. 2. the processor hid1 values only represent the multiplier of the processor?s pll (memory to processor multiplier), thus mul- tiple pc8240 pll_cfg[0 ? 4] values may have the same processor hid1 value. this implies that system software cannot read the hid1 register and associate it with a unique pll_cfg[0 ? 4] value. 3. pll_cfg[0 ? 4] settings not listed (00110, 01001, 01011, 01101, 01111, 10001, 10011, 10101, 10111, 11001, and 11011) are reserved. 4. in pll bypass mode, the pci_sync_in input signal clocks the internal processor directly, the peripheral logic pll is dis- abled, and the bus mode is set for 1:1 (pci:mem) mode operation. this mode is intended for factory use only. the ac timing specifications given in this document do not apply in pll bypass mode. table 19. pc8240 microprocessor pll configuration ref pll_ cfg [0 ? 4] (1)(3) cpu hid1 [0 ? 4] (2) 200 mhz part (9) ratios (4)(5) pci clock input (pci_ sync_in) range (1) (mhz) periph logic/ mem bus clock range (mhz) cpu clock range (mhz) pci to mem (mem vco) multiplier mem to cpu (cpu vco) multiplier 0 00000 00110 25 ? 26 75 ? 80 188 ? 200 3 (6) 2.5 (5) 1 00001 tbd not usable 3 (6) 3 (6) 2 00010 tbd 50 ? 56 (6) 50 ? 56 100 ? 112 1 (4) 2 (8) 3 00011 tbd bypass bypass 2 (8) 4 00100 00101 25 ? 28 (6) 50 ? 56 100 ? 113 2 (8) 2 (8) 5 00101 tbd bypass bypass 2.5 (5) 7 00111 tbd bypass bypass 3 (6) 8 01000 11000 33 (7) ?56 (6) 33 ? 56 100 ? 168 1 (4) 3 (6) a 01010 tbd not usable 2 (4) 4.5 (9) c 01100 00110 25 ? 40 50 ? 80 125 ? 200 2 (4) 2.5 (5) e 01110 11000 25 ? 33 50 ? 66 150 ? 200 2 (4) 3 (6) 10 10000 00100 25 ? 33 75 ? 100 150 ? 200 3 (6) 2 (4) 12 10010 00100 33 (8) ? 66 50 ? 100 100 ? 200 1.5 (3) 2 (4) 14 10100 11110 25 ? 28 50 ? 56 175 ? 200 2 (4) 3.5 (7) 16 10110 11010 25 50 200 2 (4) 4 (8) 18 11000 11000 25 ? 26 62 ? 65 186 ? 200 2.5 (5) 3 (6) 1a 11010 11010 50 50 200 1 (2) 4 (8) 1c 11100 11000 3 ? 44 50 ? 66 150 ? 200 1.5 (3) 3 (6) 1d 11101 00110 33 (8) ? 53 50 ? 80 125 ? 200 1.5 (3) 2.5 (5) 1e 11110 tbd off off 1f 11111 tbd off off
35 pc8240 2149a?hirel?05/02 5. in clock off mode, no clocking occurs inside the pc8240 regardless of the pci_sync_in input. 6. limited due to maximum memory vco = 225 mhz. 7. limited due to minimum cpu vco = 200 mhz. 8. limited due to minimum memory vco = 100 mhz. 9. range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for clarity. system design information this section provides electrical and thermal design recommendations for successful application of the pc8240. pll power supply filtering the avdd, avdd2, and lavdd power signals are provided on the pc8240 to provide power to the peripheral logic/memory bus pll, the 603e processor pll, and the sdram clock delay-locked loop (dll), respectively. to ensure stability of the internal clocks, the power supplied to the avdd, avdd2, and lavdd input signals should be fil- tered of any noise in the 500 khz to 10 mhz resonant frequency range of the plls. a separate circuit similar to the one shown in figure 26 using surface mount capacitors with minimum effective series inductance (esl) is recommended for each of the avdd, avdd2, and lavdd power signal pins. consistent with the recommendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacitors of equal value are recommended over using multi- ple values. the circuits should be placed as close as possible to the respective input signal pins to minimize noise coupled from nearby circuits. routing directly as possible from the capacitors to the input signal pins with minimal inductance of vias is important but pro- portionately less critical for the lavdd pin. figure 26. pll power supply filter circuit power supply voltage sequencing the notes in table 3 on page 8 contain cautions illustrated in figure 2 on page 9 about the sequencing of the external bus voltages and internal voltages of the pc8240. these cautions are necessary for the long term reliability of the part. if they are violated, the electrostatic discharge (esd) protection diodes will be forward biased and excessive current can flow through these diodes. figure 2 shows a typical ramping voltage sequence where the dc power sources (voltage regulators and/or power supplies) are connected as shown in figure 27. the voltage regulator delay shown in figure 2 can be zero if the various dc voltage levels are all applied to the target board at the same time. the ramping voltage sequence shows a scenario in which the vdd/avdd/avdd2/lavdd power plane is not loaded as much as the ovdd/gvdd power plane and thus vdd/avdd/avdd2/lavdd ramps at a faster rate than ovdd/gvdd. if the system power supply design does not control the voltage sequencing, the circuit of figure 27 can be added to meet these requirements. the mur420 diodes of figure 27 control the maximum potential difference between the 3.3 bus and internal voltages on power-up and the 1n5820 schottky diodes regulate the maximum potential difference on power-down. vdd avdd, avdd2, or lavdd 2.2 f 2.2 f gnd low esl surface mount capacitors 10 k ?
36 pc8240 2149a?hirel?05/02 figure 27. example voltage sequencing circuits power supply sizing the power consumption numbers provided in table do not reflect power from the ov dd and gvdd power supplies which are nonnegligible for the pc8240. in typical application measurements, the ov dd power ranged from 200 to 600 mw and the gvdd power ranged from 300 to 900 mw. the ranges? low end power numbers were results of the pc8240 performing cache resident integer operations at the slowest frequency combi- nation of 33:66:166 (pci:mem:cpu) mhz. the ovdd high end range?s value resulted from the pc8240 performing continuous flushes of cache lines with alternating ones and zeroes to pci memory. the gvdd high end range?s value resulted from the pc8240 operating at the fastest frequency combination of 66:100:200 (pci:mem:cpu) mhz and performing continuous flushes of cache lines with alternating ones and zeroes on 64-bit boundaries to local memory. decoupling recommendations due to the pc8240?s dynamic power management feature, large address and data buses, and high operating frequencies, the pc8240 can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the pc8240 system, and the pc8240 itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decou- pling capacitor at each vdd, ovdd, gvdd, and lvdd pin of the pc8240. it is also recommended that these decoupling capacitors receive their power from separate vdd, ovdd, gvdd, and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should have a value of 0.1 f. only ceramic smt (surface mount technology) capacitors should be used to minimize lead inductance, preferably 0508 or 0603, oriented such that connections are made along the length of the part. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd, ovdd, gvdd, and lvdd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors ? 100 ? 330 f (avx tps tantalum or sanyo oscon). connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ovdd. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external vdd, ovdd, gvdd, lvdd and gnd pins of the pc8240. the pci_sync_out signal is intended to be routed halfway out to the pci devices and then returned to the pci_sync_in input of the pc8240. + 5v source + 3.3v source + 5v + 3.3v + 3.3v mur420 mur420 in5820 in5820 + 2.5v + 2.5v + 2.5v source
37 pc8240 2149a?hirel?05/02 the sdram_sync_out signal is intended to be routed halfway out to the sdram devices and then returned to the sdram_sync_in input of the pc8240. the trace length may be used to skew or adjust the timing window as needed. see motorola appli- cation note an1794/d for more information on this topic. pull-up/pull-down resistor requirements the data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up resistors on the bus. the data bus sig- nals are: dh[0 ? 31], dl[0 ? 31], and par[0 ? 7]. if the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (dl[0 ? 31], and par[4 ? 7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. for this mode, these pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible output switching. the test [0 ? 1] pins require pull-up resistors of 120 ? or less connected to ovdd. it is recommended that test2 have weak pull-up resistor (2 k ? ?10k ? ) connected to gvdd. it is recommended that the following signals be pulled up to ovdd with weak pull-up resistors (2 k ? ?10k ? ): sda, scl, smi ,sreset , tben, chkstop_in ,test3,and test4. it is recommended that the following pci control signals be pulled up to lvdd with weak pull-up resistors (2 k ? ?10k ? ): devsel ,frame ,irdy ,lock ,perr ,serr ,stop , and trdy . the resistor values may need to be adjusted stronger to reduce induced noise on specific board designs. the following pins have internal pull-up resistors enabled at all times: req [0 ? 3], req4 /da4,tck,tdi,tms,andtrst . see table 1, ?pc8240 pinout listing,? on page 3 for more information. the following pins have internal pull-up resistors enabled only while device is in the reset state: gnt4 /da5, dl0, foe ,rcs0 ,sdras ,sdcas , cke, as ,mcp ,maa[0? 2], pmaa[0 ? 2]. see table 1, ?pc8240 pinout listing,? on page 3 for more information. the following pins are reset configuration pins: gnt4 /da5,dl0,foe , rcs0 ,cke,as , mcp ,qack /da0, maa[0 ? 2], pmaa[0 ? 2], and pll_cfg[0 ? 4]/da[10 ? 6]. these pins are sampled during reset to configure the device. resetconfigurationpinsshouldbetiedtogndvia1k ? pull-down resistors to ensure a logic zero level is read into the configuration bits during reset if the default logic one level is not desired. any other unused active low input pins should be tied to a logic one level via weak pull- up resistors (2 k ? ?10k ? ) to the appropriate power supply listed in table 3 on page 8. unused active high input pins should be tied to gnd via weak pull-down resistors (2 k ? ?10k ? ).
38 pc8240 2149a?hirel?05/02 jtag configuration signals boundary scan testing is enabled through the jtag interface signals. (bsdl descrip- tions of the pc8240 are available on the internet at www.mot.com/sps/powerpc/teksupport/tools/bsdl/) the trst signal is optional in the ieee 1149.1 specification but is provided on all powerpc implementations. while it is possible to force the tap controller to the reset state using only the tck and tms signals, more reliable power-on reset performance will be obtained if the trst signal is asserted during power-on reset. since the jtag interface is also used for accessing the common on-chip processor (cop) function of powerpc processors, simply tying trst to hrst_cpu/hrst_ctrl is not practical. note that the two hard reset signals on the pc8240 (hrst_cpu and hrst_ctrl) must be asserted and negated together to guarantee normal operation. the common on-chip processor (cop) function of powerpc processors allows a remote computer system (typically a pc with dedicated hardware and debugging software) to access and control the internal operations of the processor. the cop interface con- nects primarily through the jtag port of the processor, with some additional status monitoring signals. the cop port requires the ability to independently assert hrst_cpu/hrst_ctrl or trst in order to fully control the processor. if the target system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches, then the cop reset signals must be merged into these signals with logic. the arrangement shown in figure 28 allows the cop to independently assert hrst_cpu/hrst_ctrl or trst while ensuring that the target can drive hrst_cpu/hrst_ctrl as well. the shown cop header, adds many benefits includ- ing breakpoints, watchpoints, register and memory examination/modification and other standard debugger features are possible through this interface. availability of these fea- tures can be as inexpensive as an unpopulated footprint for a header to be added when needed.
39 pc8240 2149a?hirel?05/02 figure 28. cop connector diagram from target board sources (if only) cop header sreset hreset pc8240 sreset hrst_cpu hrst_ctrl ckstp_in tms tdo tdi tck qack1 nc 12 nc 10 nc tck 2 7 tdi 3 tdo 1 tms 9 ckstp_in 8 vdd_sense 6 trst 4 12 34 56 78 9 10 11 12 13 key no pin 15 16 sreset 11 hreset 13 key 144 cop connector physical pin out 153 52 16 ovdd 10 k ? 10 k ? 10 k ? 10 k ? 1.5 k ? 10 k ? 10 k ? 10 k ? 2 k ? ovdd ovdd ovdd ovdd ovdd ovdd ovdd trst gnd notes: 2. run/stop normally found on pin 5 of the cop header is not implemented on the pc8240. connect pin 5 of the cop header to ovdd with a 10k pull-up resistor. 1. qack is an output on the pc8240 and is not required at the cop header for emulation. 3. ckstp_out normally found on pin 15 of the cop header is not implemented on the pc8240. connect pin 15 of the cop header to ovdd with a 10k pull-up resistor. 4. pin 14 is not physically present on the cop header. 5. component not populated.
40 pc8240 2149a?hirel?05/02 the cop interface has a standard header for connection to the target system, based on the 0.025? square-post 0.100? centered header assembly (often called a ?berg? header). the connector typically has pin 14 removed as a connector key, as shown in figure 28. there is no standardized way to number the cop header shown in figure 28 on page 39; consequently, many different pin numbers have been observed from emulator ven- dors. some are numbered top-to-bottom then left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin one (as with an ic). regardless of the numbering, the signal placement recommended in is common to all known emulators. definitions datasheet status description life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. atmel customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify atmel for any damages resulting from such improper use or sale. table 20. datasheet status datasheet status validity objective specification this datasheet contains target and goal specifications for discussion with customer and application validation. before design phase target specification this datasheet contains target or goal specifications for product development. valid during the design phase preliminary specification -site this datasheet contains preliminary data. additional data may be published later; could include simulation results. valid before characterization phase preliminary specification -site this datasheet contains also characterization results. valid before the industrialization phase product specification this datasheet contains final product specification. valid for production purposes limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification.
41 pc8240 2149a?hirel?05/02 differences with commercial part ordering information table 21. differences with commercial part commercial part industrial part temperature range tc = 0 to 105c tc = -40 to 110c or tc = -40 to 125 power consumption use a 1.25 factor to calculate at low temperature (-55c) spec 13a (output hold) 1 ns 0.5 ns pc8240 v tp u e type (pcx8240 if prototype) package tp: tbga screening level (1) u: upscreening revision level extended temperature tc = -40 c to 125 c temperature range: t c v: -40 c, +110 c max internal processor speed (1) 200: 200 mhz 200 note: 1. for availability of the different versions, contact your atmel sale office. (zd3)
printed on recycled paper. ? atmel corporation 2002. atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standard warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not authorized for use as critical components in life support devices or systems. atmel headquarters atmel operations corporate headquarters 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 487-2600 europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel (41) 26-426-5555 fax (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimhatsui east kowloon hong kong tel (852) 2721-9778 fax (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel (81) 3-3523-3551 fax (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel 1(408) 441-0311 fax 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel (33) 2-40-18-18-18 fax (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel (33) 4-42-53-60-00 fax (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel (44) 1355-803-000 fax (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel (49) 71-31-67-0 fax (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel 1(719) 576-3300 fax 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel (33) 4-76-58-30-00 fax (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 2149a?hirel?05/02 0m atmel ? is the registered trademark of atmel. the powerpc names and the powerpc logotype are trademarks of international business machines corpora- tion, used under license therform. motorola is the registered trademark of motorola, inc. other terms and product names may be the trademarks of others.

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